Lithography - Abstracts and Biographies
Rolf Seltmann, Lithography Fellow
GLOBALFOUNDRIES
Biography
Rolf Seltmann is a Lithography Fellow at GLOBALFOUNDRIES’s Fab1 in Dresden, Germany. He is responsible for lithography development activities for both 32nm and 28nm technology nodes. He acts as a GLOBALFOUNDRIES representative in the Technology Advisory Board of the Advanced Mask Technology Center (AMTC) in Dresden. Before his role at GLOBALFOUNDRIES he served for more than 10 years at AMD’s Fab30 and Fab36 in Dresden. There he was in charge for the introduction of Step&Scan systems of 248nm and 193nm wavelength, including immersion. Furthermore, he worked on the characterization and reduction of the impact of process variations (CD, overlay) on the performance of state of the art microprocessors. Before joining AMD, Rolf worked as Project Manager at Fraunhofer Institute for Microelectronic Circuits and Systems in Dresden.
Beyond Immersion - Patterning Enablers for the Next Decade
Colin J. Brodsky, Manager and Senior Technical Staff Member, Patterning Process Development
IBM Systems and Technology Group
Biography
Dr. Brodsky joined the IBM Semiconductor Research and Development Center in 2001 after earning his Ph.D. in chemical engineering from the University of Texas at Austin and his B.S. in chemical engineering from Carnegie Mellon University. Since joining IBM, he has been responsible for the development of a broad range of lithography processes as a process development engineer for the 90-nm and 65-nm technology nodes, and since 2006, as manager of lithography and integrated patterning teams for the 45 and 32 nm SOI technology nodes. Alongside his management role, he has continued to maintain technical interests in collaborative development of new experimental designs and characterization techniques that exploit advanced process yield learning methodologies, productivity improvements with early immersion lithography manufacturing toolsets, implementation of systematic patterning variability analysis techniques to improve process window optimization and centering efforts, and leading efforts to drive down patterning-related micro-bridging defects across multiple technologies in IBM’s 300 mm fab. He was appointed to IBM’s Senior Technical Staff in 2011 and currently holds in excess of 20 U.S. patents.
Abstract
Immersion lithography continues to serve as the workhorse lithography solution for technologies coming into production. While the industry has reached near-consensus that EUV lithography is inevitable, achieving widespread cost-effective volume production remains many years away. In this gap, multi-patterning solutions are extending the prospects for immersion lithography, albeit at an increasingly challenging production cost and end-to-end cycle time. Meeting this challenge requires innovation on many fronts from design to process. Fundamental assumptions about how we do lithography have been turned on end, such as the introduction of negative-tone solvent-based develop. Closer collaboration will be required between lithography and etch engineers to enable the increasingly multi-dimensional control required for multi patterning schemes. Evaluating such options will be increasingly dependent on electrical insights gleaned through technology qualification vehicles alongside more accessible metrics such as CD and optical inspection capabilities. This presents a rich climate for collaborative innovation between IDMs and suppliers to work towards both disruptive innovations, as well as solutions that help bridge the gap to a widely anticipated manufacturable, cost-effective EUV lithography solution.
Design and Process Challenges with Double Patterning for 20nm logic
Pierre-Jérôme Goirand, Lithography R&D Manager Crolles 300
STMicroelectronics
Biography
ST Microelectronics Crolles
• 03/2007 Lithography R&D Manager Crolles 300
• 08/2005 Advanced Patterning Manager
• 07/2003 Lithography Engineering Manager Crolles 300
• 05/1999 Lithography R&D Manager Crolles 200
MANNESMANN DEMATIC POSTAL AUTOMATION (Equipment Manufacturer)
• 04/1998 Prototypes Test Team Manager
PHILIPS SEMICONDUCTORS Crolles
• 07/1996 Lithography Industrial Owner Crolles200
PHILIPS SEMICONDUCTORS Caen and LEP Paris
• 03/1993 Lithography Development Manager Caen
• 08/1990 Process-Equipment Engineering Manager for Metal and Diel deposition Caen
• 09/1987 Development owner for Metal and Diel deposition for CMOS Caen
• 03/1984 Technology developments for electro-optical devices on III-V materials LEP
Education :
• ‘Ingénieur Génie Physique’ diploma graduated from Institut Polytechnique Grenoble 1983
Abstract
Double patterning is used today for 45 and 28 nm technologies as a basic enhancement technology, for cutting end of gates in dense memory cells. This helps in patterning difficult gate to gate spaces, but does not aim to gain on pitch of gates.
For 20nm technology, as EUV lithography will not be ready, and resolution of 193nm immersion lithography is too much limited with single patterning, the use of real double patterning will be mandatory to print required pitches.
Mainly 2 double patterning techniques are being evaluated for 20nm: double litho-etch (LELE), and spacer deposition technique (SIT). These 2 techniques are the most promising in achieving 2x device density compared to 28nm, and in being industrialisable.
Whereas LELE presents some patterning fidelity qualities, and design advantages, it is very critical in terms of pattern placement and dimensional control; SIT relaxes pattern placement constraints, but at the expense of a slightly less fidel patterning, and some restrictive design rules.
The technical choice is to be made in the course of next year, for dense interconnection pitch of 64nm, keeping in mind that for interconnections, reliability could put a high constraint on pattern placement.
These 2 techniques and their associated challenges both on the design and the process aspect will be presented.
Multi e-beams (ML2) Opportunities in Advanced Lithography
Serge Tedesco, Program Manager
CEA-LETI
Biography
Dr Tedesco obtained a PhD in Experimental Nuclear Physics from Grenoble University (F) in 1979.
From 1980 to 1981: Work on surface analysis equipment development (ESCA) at Riber SA in Paris.
From 1981 to 1987 : Work on electron beam lithography technology at Varian Lithography Product Division in Gloucester Mass. (USA) where he was first responsible for System integration of the raster scan e-beam systems and then Engineering manager .
In 1987 he joined the CEA-LETI laboratories in Grenoble to take in charge e-Beam lithography and consequently all Advanced Lithography activities.
Since 2003 he manages CEA-LETI lithography strategy and programs as Lithography Program manager.
Dr Tedesco has authored or co-authored more than 110 papers in the field of lithography and he is a Program committee member of the major International lithography conferences. Dr Tedesco has been involved in numerous European projects both as project leader and expert.
Abstract
Since the 1980s, the optical mask based solution remains the undisputed driver of the semiconductor industry. Its technological leadership could be maintained through the years thanks to key successive improvements like wavelength reduction, numerical aperture increase, take off of chemically amplified resists, introduction of immersion principle, optical proximity correction and double patterning techniques. However, linked to these constant innovations, this technique becomes increasingly complex and expensive every generation. And this trend will not slow down, with the introduction of EUV which is still affected by development difficulties as well as tool and mask very high cost forecasts.
With such perspectives and the willingness of the integrated circuit makers to push manufacturing costs down, Mask Less Lithography (ML2) represents a promising option to deal with this present concern. The key benefit relies to the production price reduction for low and mid volume applications. Furthermore, this technique appears quite attractive for coping with the increasing difficulties relative to the patterning of critical levels as the contact layers.
CEA-LETI with MAPPER has launched in 2009 an international industrial program, called IMAGINE, on Maskless Lithography for 22nm and sub-22 nm IC manufacturing. This program is performed around a multi e-beams Mapper platform install within CEA-Leti premises. The IMAGINE program cover a range of topics, including tool assessment, patterning and process integration, data handling, proximity effect corrections and cost of ownership studies.
The aim of this paper is to detail the content and the objectives of the ML2 program at CEA-LETI and to present the main achievements on both the tool and its infrastructure toward a High Volume Manufacturing ML2 solution.
Pushing 193i Lithography by Joint Optimization of Layout and Lithography
Peter De Bisschop, Principle Scientist, Lithography Department
IMEC
Biography
P. De Bisschop obtained his Ph.D. in Atomic Physics in 1984, at the University of Leuven, in Belgium. In 1986, he joined imec, where he worked until 1995 in the Materials-Analysis group on the development of a laser-assisted SIMS technique. In 1995 he move to the Lithography department, where he worked on stepper and scanner assessment, with a focus on imaging-related topics such as lens aberrations, stray light and optical proximity, both through simulations and experiments. He was also involved in early 157 nm (hard pellicle), immersion (bubble-defects) and EUV (mask shadowing) specific topics. His current activities are on the interaction between layout and lithography and design rules, for pushing 193i lithography to its limits, in particular for the case of SRAM and Logic.
Abstract
Even though technology scaling is no longer carried by a succession of new lithography tools with gradually increasing NA or decreasing wavelength (at least in the optical lithography field), semiconductor industry intends to continue the scaling trends that have been followed during the past two decades. This forces lithography to operate very close to the resolution limit of the exposure tools, which is workable only by the introduction of new approaches such as double patterning but also by placing increasing restrictions on the patterns that need to be printed. Such layout restrictions have been initially introduced in the gate level, but become increasingly important for all layers. The trend is to move as much as possible to unidirectional layers with cut-approach.
This presentation will illustrate this evolution and discuss how including the layout in the lithography optimization process can extend the applicability of 193i.
Evaluation of Technology Options by Lithography Simulation
Andreas Erdmann, Head of Lithography Simulation
Fraunhofer IISB
Biography
Andreas Erdmann received his PhD degree with specialization in applied optics from the Friedrich-Schiller-University of Jena, Germany, in 1988. In 1995 he joined the Fraunhofer Institute ISiT, where he started his activities in the field of lithography simulation. Since 1999 he is head of the Lithography Simulation Group in the semiconductor technology simulation department at Fraunhofer IISB. His fields of research include simulation of optical lithography, computational electrodynamics, microelectronic process technology and modern optics. Dr. Erdmann contributed to the development of several advanced lithography simulators including the Development and research LiTHOgraphy simulator Dr.LiTHO.
Abstract
Physical lithography simulation has become an established tool for the development and optimization of lithographic processes in semiconductor integrated circuit (IC) fabrication. New technologies like double patterning and EUV lithography require the consideration of additional effects and appropriate model extensions. For example, lithography simulation can be used to explore interaction effects between lithography steps in double patterning, to investigate the printing of multilayer defects on EUV masks, and to perform early investigations of the imaging performance of EUV systems with a wavelength of 6.5 nm. Nowadays, an increased interest in lithography modeling for applications beyond standard IC fabrication can be seen.
Directed Self-assembly of Block-Copolymer for CMOS Technology
Raluca Tiron
MINATEC
Biography
Raluca Tiron received her PhD degree in molecular magnetism from University Joseph Fourier France in 2004. In 2004 she joint lithography group at CEA-LETI working on eBeam lithography. In 2005 she integrates Resist Expertise Center, working on advanced lithography process development, resist characterisation and mechanisms comprehension in 193 nm lithography. Her current research interest focuses on directed self assembly of block copolymers.
Abstract
Density multiplication of patterned templates by directed self-assembly (DSA) of block copolymers stands out as a promising alternative to overcome the limitation of conventional lithography. To date, various DSA methods have been exploited for lateral ordering of block copolymer self assembled thin films. Among them, direct self assembly on chemical pre-patterns and graphoepitaxy are two predominant approaches to generate density multiplication of patterned templates using block copolymers. Today the capability of DSA to be integrated with state-of-the-art 193nm lithography has been demonstrated and the challenge is now at the implementation of DSA within a 300 mm baseline.
In this paper, we will detail the two DSA approaches, graphoepitaxy and surface chemical modification, and the advantages and limitations of both techniques will be discussed. We will conclude on the high potential of DSA to be integrated into the conventional CMOS lithography process in order to achieve high resolution and pattern density multiplication, at a low cost.
Wafer Chucks for Immersions- and EUV–Lithography
Sven Götze, Project Manager, Product Engineering Semicon,
Berliner Glas KGaA Herbert Kubatz GmbH & Co.
Biography
Sven Goetze was born in July, 1969. He majored in plasma physics at the Ernst-Moritz-Arndt University in Greifswald. After his study he spent six years developing capillary and z-pinch discharges for laser application, three years of them at a French institute in Orléans, France. Since 2001 he has been working in the Semicon business. Until 2010 he was employed at XTREME technologies GmbH, a company developing and manufacturing light sources for the EUV lithography market. There he was responsible for the continuous improvement process (CIP).
2010 Sven Goetze joined Berliner Glas KGaA, Herbert Kubatz GmbH & Co.. Currently he is leading a product development team mainly developing and manufacturing customized clamps for the lithography market as well as for the photovoltaic cell or the OLED market or others.
Abstract
BERLINER GLAS is a premier supplier of optical key components, assemblies and integrated systems to leading semiconductor equipment manufacturers worldwide. BERLINER GLAS develops and manufactures high precision wafer chucks for extreme UV and deep UV lithographic systems. The presentation focuses on working principles, materials, manufacturing processes, special requirements as well as test and qualification procedures for state-of-the-art vacuum- and electrostatic chucks.
Over-Actuation for a 450 mm Wafer Chuck
Dick Laro, dr.ir. / System Architect
MI-Partners
Biography
Dick Laro received a PhD degree in the mechatronic design of a magnetically levitated positioning system from the Delft University of Technology in 2009. In 2009 he joined MI-Partners as a system architect where he is responsible for the development of high tech mechatronic systems. Next to the development of customer specific solutions, he performs research on new actuation concepts for high accuracy systems.
Abstract
Wafers with a diameter of 450 mm are one of the future challenges for the semiconductor manufacturing industry. The increased wafer size leads to an increased size of the positioning stages and chucks. Because of the desire to keep internal flexible modes at high frequencies, the wafer chuck tends to increase significantly in thickness and mass. To maintain throughput, higher acceleration forces are needed to accelerate these heavier chucks. Large actuation forces cause unwanted heat generation and excitation of accurate machine components. An alternative solution is to apply over-actuation to these positioning systems. In over-actuation more actuators are used than the unconstrained degrees of freedom. While over-actuation promises a reduction of weight at high levels of performance, it does so at the cost of additional control complexity. In this presentation a method of over-actuation developed by MI-Partners is presented where the added complexity is limited and a significant step in performance is made.
Improving Immersion Lithography Cells OEE: Deploying An Effective Process
Michael Romanenko,
MAX I.E.G
Abstract
The presentation describes a case study of ArF Immersion lithography cells' productivity improvement. The case study covers the long term OEE improvements and day to day throughput optimization.
