Advanced Packaging Conference (APC)
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Power and Interconnects Innovations Enabling AI System Performance
Advanced packaging (AP) and test innovations are key to sustaining system-level performance scaling as traditional device scaling reaches its limits. In 2026, AP is central to next-generation electronics, enabling higher integration density, better power efficiency, and improved thermal and signal performance across HPC, AI, automotive, 5G/6G, and edge applications.
Through 2.5D/3D integration, chiplet architectures, heterogeneous integration, and advanced substrates and interconnects, the industry can significantly increase compute, bandwidth, and functionality while reducing power consumption. Innovations in materials, backside power delivery, fine-pitch interconnects, and chip–package–system co-design are becoming critical differentiators.
At the same time, sustainability and supply chain resilience are increasingly important, with a focus on lifecycle impact, resource efficiency, circularity, and regional manufacturing ecosystems. Advanced packaging is evolving from a back-end process into a strategic enabler of system architecture and value chain differentiation.
At this year’s Advanced Packaging Conference (APC), we bring together leading experts from academia, industry, and government to discuss the latest trends, challenges, and innovations shaping the field.
SEMI Europe Advanced Packaging Conference (APC) Committee:
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Engagement Opportunity – APC–FMF Expo
Exhibit at the APC–FMF Expo
Messe Munich – International Conference Center (ICM), Foyer 1st Floor
Wednesday, 11 November 2026
Day 2 of SEMICON Europa
Secure your turnkey booth alongside the paid Advanced Packaging Conference (Room 14a) and Fab Management Forum (Room 14c).
Staggered breaks and lunch periods maximize face-to-face networking with a paid-access audience from both conferences. During concurrent APC and FMF sessions, your team has built-in time to visit the full SEMICON Europa exhibition on the main showground.
Targeted access. Dual opportunity. Stronger ROI.
Agenda
Additional posters that will be displayed in the Networking area during the conference hours:
- Die-to-Package ratios unmasked: correlating package area, type, and die size for enhanced LCA, T. Rola, TechInsights
- Applying Manufacturing Digital Twins for Advanced Packaging: AI-Driven Yield Optimization Using Equipment, Metrology, and Test Data, H. Dudek, Siemens EDA
- A Predictive Simulation Framework for Direct Wafer Bonding Process Optimization Using Calibrated Interfacial Interactions, A. Goel, Dassault Systèmes
- Efficiency of Kelvin Source Wire Bonding with 8mil wire to resistance, inductance, and reliability improvement of Silicon Carbide Discrete Package TO-247 4L, H. Malveda, Nexperia Germany GmbH
- Pre-Mold Auto Optical Inspection Cost Avoidance Through Implementation of Aluminum Wedge Bonding In-line Non-Destructive Pull Test Solutions in Silicon Carbide, H. Malveda, Nexperia Germany GmbH
- System-Level Optimization of X-ray Nano-CT and Laminography for Advanced Packaging Inspection, J. Hållstedt, Excillum
- Co-Packaged Optics: Bridging Semiconductor and Optical Packaging with DELO's Proven Advanced Materials Portfolio, O. Matyssek, DELO
- Enabling efficient and sustainable wet processes for advanced packaging technologies, L. Céleste, Technic France
- System-level co-design from CHIPS to PACKAGE using PLATFORM, S. Joshi, Dassault Systèmes
- Full Field Lithography: Unlocking the expansion of the System on Wafer Plattform, L. Michels, SUSS MicroTec Solutions GmbH Co. KG
- Transforming Media Delivery into Process Intelligence Infrastructure: Enabling Smart CMP Through Inline Monitoring of Ceria Slurry Chemistry, R. Morgan, Exentec
- Liquid-Assisted USP Laser Structuring of Silicon Carbide Heat Spreader Architectures for Advanced Packaging, C. Keil, Lidrotec GmbH
- Software-Driven Strategies for Advanced Multi-Die Patterning in Digital Lithography, K. Varga, EV Group
- RDL-First FOWLP: Process, Design, and System Validation for Reliable Multi-Chiplet Integration at 77 GHz, P. Fromme, Fraunhofer IZM-ASSID